Serial Port Complete - Latest Microcontroller projects

(lily) #1
Designing RS-485 Links and Networks

TIA-485-A says that RS-485 drivers must be able to drive 32 unit loads plus a
parallel termination of 60Ω. The total load, including the driver, receivers, and
terminations, must be 54Ω or greater. On a full-duplex line, each termination
resistor has its own pair of wires, so each driver sees a resistance of 120Ω. In a
cable with two termination resistors across the same pair of wires, the parallel
combination of two 120Ω resistors is 60Ω. The input impedance of 32 receivers
at 1 unit load each decreases the total resistance of the load slightly, while the
output resistance of the driver and the series resistance of the lines increase the
total resistance of the load.

033   3
1  


You don’t have to understand why transmission lines behave as they do to
design a system that works. But for the curious, the following is an introduction
to transmission-line theory without attempting mathematical proofs.
A transmission line has two wires, one to carry the current from the driver to
receiver and another to provide a return path back to the driver. An RS-485 sys-
tem is a little more complex because it has two signal wires that share a termina-
tion plus a ground return, but the basic principles are the same.
In one sense, there’s nothing different about how long and short lines behave.
The same laws of physics apply whether the driver is slow or fast and whether
the signals travel a short or long distance. Both long and short lines can have
voltage and current reflections due to an impedance mismatch.

Table 7-2: RS-485 lines can use any of several termination options.


+    
  

none no added components, low power suitable only for short lines with
slow drivers
parallel end effective at high bit rates high power
series low power suitable only for 2-node lines
AC low power suitable only for low bit rates,
short cables
parallel with open-circuit
biasing

ensures valid logic level when
open

high power, requires 2 additional
resistors per bus
parallel with open and
short-circuit biasing

ensures valid logic level when
open or shorted

requires 4 additional resistors per
node
Free download pdf