Chapter 4
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The TIA-232 standard includes timing specifications that RS-232-compliant
chips must meet.
The specified maximum slew rate limits the bit rate of the interface. Slew rate is
a measure of how fast the voltage changes when the output switches and
describes an output’s instantaneous rate of voltage change. The slew rate of an
RS-232 driver must be 30 V/μs or less. Limiting the slew rate improves signal
quality by eliminating problems due to voltage reflections that occur on long
lines that carry signals with fast rise and fall times. Chapter 7 has more on this
topic.
At 30 V/μs, an output requires 0.3 μs to transition from +5V to -5V. RS-232’s
specified maximum bit rate is 20 kbps, which translates to a bit width of 50 μs,
or 16 times as long as the switching time at the fastest allowed slew rate.
In reality, because UARTs read inputs near the middle of the bit and most tim-
ing references are very accurate, you can often safely use bit widths as short as
5–10 times the switching time. Some interface chips are rated for operation at
120 or 250 kbps while maintaining slew rates that comply with the standard.
Besides having a maximum switching speed, RS-232 drivers must also meet
minimum standards to ensure that signals don’t linger in the undefined region
between logic states when switching. For control signals and other signals at 40
bps and lower, the line must spend no more than 1 ms in the transition region
between a valid logic 0 and logic 1. For other data and timing signals, the limit
is 4% of a bit width, which works out to 2 μs at 20 kbps or 0.33 μs at 120 kbps.
An output that switches between -5V and +5V in 0.33 μs is changing at the
specified upper (fastest) limit for the slew rate. The signals’ rise and fall times
should also be as nearly equal as possible.
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Many microcontrollers have asynchronous serial ports that use TTL logic levels
based on a 5V power supply or CMOS logic levels based on a power supply of
3V, 3.3V, or 5V. Interfacing to an RS-232 port requires converting between
these voltages and RS-232 voltages.
Table 4-3 shows logic levels for different chip families and supply voltages. 5V
logic refers to the logic levels used by TTL or CMOS logic chips powered by a
single +5V power supply with signal voltages referenced to ground. 3V and
3.3V logic refer to the logic levels used by CMOS logic chips powered by a sin-