PRELIMINARY BETA. NOT FOR REDISTRIBUTION.
The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.
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Chapter 1: Connector Menu 72 pin SO DIMM Connector
72 pin SO DIMM
SO DIMM=Small Outline Dual Inline Memory Module
(At the computer)72 PIN SO DIMM at the computer.PinNon-ParityParityDescription
1 VSS VSS Ground
2 DQ0 DQ0 Data 0
3 DQ1 DQ1 Data 1
4 DQ2 DQ2 Data 2
5 DQ3 DQ3 Data 3
6 DQ4 DQ4 Data 4
7 DQ5 DQ5 Data 5
8 DQ6 DQ6 Data 6
9 DQ7 DQ7 Data 7
10 VCC VCC +5 VDC
11 PD1 PD1 Presence Detect 1
12 A0 A0 Address 0
13 A1 A1 Address 1
14 A2 A2 Address 2
15 A3 A3 Address 3
16 A4 A4 Address 4
17 A5 A5 Address 5
18 A6 A6 Address 6
19 A10 A10 Address 10
20 n/c PQ8 Data 8 (Parity 1)
21 DQ9 DQ9 Data 9
22 DQ10 DQ10Data 10
23 DQ11 DQ11Data 11
24 DQ12 DQ12Data 12
25 DQ13 DQ13Data 13
26 DQ14 DQ14Data 14
27 DQ15 DQ15Data 15
28 A7 A7 Address 7
29 A11 A11 Address 11
30 VCC VCC +5 VDC
31 A8 A8 Address 8
32 A9 A9 Address 9
33 /RAS3 RAS3Row Address Strobe 3
34 /RAS2 RAS2Row Address Strobe 2
35 DQ16 DQ16Data 16
36 n/c PQ17Data 17 (Parity 2)
37 DQ18 DQ18Data 18
38 DQ19 DQ19Data 19
39 VSS VSS Ground
40 /CAS0 CAS0Column Address Strobe 0
41 /CAS2 CAS2Column Address Strobe 2
42 /CAS3 CAS3Column Address Strobe 3
43 /CAS1 CAS1Column Address Strobe 1
44 /RAS0 RAS0Row Address Strobe 0
45 /RAS1 RAS1Row Address Strobe 1
46 A12 A12 Address 12
47 /WE WE Read/Write