PRELIMINARY BETA. NOT FOR REDISTRIBUTION.
The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.
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Chapter 1: Connector Menu EISA (Tech) Connector
EISA (Technical)
This section is currently based solely on the work by Mark Sokos.
This file is intended to provide a basic functional overview of the EISA Bus, so that hobbyists
and amateurs can design their own EISA compatible cards.It is not intended to provide complete coverage of the EISA standard.
EISA is an acronym for Extended Industry Standard Architecture. It is an extension of the
ISA architecture, which is a standardized version of the bus originally developed by IBM for
their PC computers. EISA is upwardly compatible, which means that cards originally
designed for the 8 bit IBM bus (often referred to as the XT bus) and cards designed for the
16 bit bus (referred to as the AT bus, and also as the ISA bus), will work in an EISA slot.
EISA specific cards will not work in an AT or an XT slot.The EISA connector uses multiple rows of connectors. The upper row is the same as a
regular ISA slot, and the lower row contains the EISA extension. The slot is keyed so that
ISA cards cannot be inserted to the point where they connect with the EISA signals.Signal Descriptions
+5, -5, +12, -12
Power supplies. -5 is often not implemented.
AEN
Address Enable. This is asserted when a DMAC has control of the bus. This prevents an I/O
device from responding to the I/O command lines during a DMA transfer.BALE
Bus Address Latch Enable. The address bus is latched on the rising edge of this signal. The
address on the SA bus is valid from the falling edge of BALE to the end of the bus cycle.
Memory devices should latch the LA bus on the falling edge of BALE.BCLK
Bus Clock, 33% Duty Cycle. Frequency Varies. 8.33 MHz is specified as the maximum, but
many systems allow this clock to be set to 10 MHz and higher.BE(x)
Byte Enable. Indicates to the slave device which bytes on the data bus contain valid data. A
16 bit transfer would assert BE0 and BE1, for example, but not BE2 or BE3.CHCHK
Channel Check. A low signal generates an NMI. The NMI signal can be masked on a PC,
externally to the processor (of course). Bit 7 of port 70(hex) (enable NMI interrupts) and bit 3
of port 61 (hex) (recognition of channel check) must both be set to zero for an NMI to reach
the cpu.CHRDY
Channel Ready. Setting this low prevents the default ready timer from timing out. The slave
device may then set it high again when it is ready to end the bus cycle. Holding this line low
for too long can cause problems on some systems. CHRDY and NOWS should not be used
simultaneously. This may cause problems with some bus controllers.CMD