PRELIMINARY BETA. NOT FOR REDISTRIBUTION.
The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.
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Chapter 1: Connector Menu EISA (Tech) Connector
Command Phase. This signal indicates that the current bus cycle is in the command phase.
After the start phase (see START), the data is transferred during the CMD phase. CMD
remains asserted from the falling edge of START until the end of the bus cycle.SD0-SD16
System Data lines. They are bidrectional and tri-state.
DAKx
DMA Acknowledge.
DRQx
DMA Request.
EX16
EISA Slave Size 16. This is used by the slave device to inform the bus master that it is
capable of 16 bit transfers.EX32
EISA Slave Size 32. This is used by the slave device to inform the bus master that it is
capable of 32 bit transfers.EXRDY
EISA Ready. If this signal is asserted, the cycle will end on the next rising edge of BCLK.
The slave device drives this signal low to insert wait states.IO16
I/O size 16. Generated by a 16 bit slave when addressed by a bus master.
IORC
I/O Read Command line.
IOWC
I/O Write Command line.
IRQx
Interrupt Request. IRQ2 has the highest priority.
LAxx
Latchable Address lines.
LOCK
Asserting this signal prevents other bus masters from requesting control of the bus.
MAKx
Master Acknowledge for slot x: Indicates that the bus master request (MREQx) has been
granted.MASTER16
16 bit bus master. Generated by the ISA bus master when initiating a bus cycle.
M/IO