PRELIMINARY BETA. NOT FOR REDISTRIBUTION.
The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.
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Chapter 1: Connector Menu EISA (Tech) Connector
Memory/Input-Output. This is used to indicate whether the current bus cycle is a memory or
an I/O operation.M16
Memory Access, 16 bit
MRDC
Memory Read Command line.
MREQx
Master Request for Slot x: This is a slot specific request for the device to become the bus
master.MSBURST
Master Burst. The bus master asserts this signal in response to SLBURST. This tells the
slave device that the bus master is also capable of burst cycles.MWTC
Memory Write Command line.
NOWS
No Wait State. Used to shorten the number of wait states generated by the default ready
timer. This causes the bus cycle to end more quickly, since wait states will not be inserted.
Most systems will ignore NOWS if CHRDY is active (low). However, this may cause
problems with some bus controllers, and both signals should not be active simultaneously.OSC
Oscillator, 14.318 MHz, 50% Duty Cycle. Frequency varies.
REFRESH
Refresh. Generated when the refresh logic is bus master.
RESDRV
This signal goes low when the machine is powered up. Driving it low will force a system
reset.SA0-SA19
System Address Lines, tri-state.
SBHE
System Bus High Enable, tristate. Indicates a 16 bit data transfer.
SLBURST
Slave Burst. The slave device uses this to indicate that it is capable of burst cycles. The bus
master will respond with MSBURST if it is also capable of burst cycles.SMRDC
Standard Memory Read Command line. Indicates a memory read in the lower 1 MB area.
SMWTC
Standard Memory Write Commmand line. Indicates a memory write in the lower 1 MB area.