PRELIMINARY BETA. NOT FOR REDISTRIBUTION.
The Hardware Book is freely distributable but is copyrighted to Joakim Ögren. It may not be modified and re-distributed without the authors permission.
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Chapter 1: Connector Menu IndustrialPCI Connector
B2 AD3 Address 3
B3 +5V +5 VDC
B4 AD8 Address 8
B5 +3,3V +3.3 VDC
B6 AD14 Address 14
B7 PAR Parity
B8 +3,3V +3.3 VDC
B9 STOP# Stop 1
B10 C/BE2# Command, Byte Enable 2
B11 V(I/O) +3.3 or +5 VDC
B12 AD21 Address 21
B13 +3,3V +3.3 VDC
B14 V(I/O) +3.3 or +5 VDC
B15 AD28 Address 28
B16 AD31 Address 31
B17 +3,3V +3.3 VDC
B18 GNT3 Grant 3
B19 RST# Reset
B20 NMI# Non Maskable Interrupt
B21 X6 Reserved (6)
B22 +5V +5 VDC :
B23 RSTIN#
B24 USB+ Universal Serial Bus (USB)(+)
C1 ACK64# Acknowledge 64 ??? 1
C2 GND Ground
C3 AD7 Address 7
C4 AD9 Address 9
C5 AD11 Address 11
C6 GND Ground
C7 SERR# System Error 1
C8 PERR# Parity Error 1
C9 DEVSEL# Device Select 1
C10GND Ground
C11AD19 Address 19
C12AD22 Address 22
C13GND Ground
C14AD25 Address 25
C15GND Ground
C16X1 Reserved (1)
C17GNT2 Grant 2
C18REQ4 Request 4 1
C19SLEEP#/SDATSleep/Serial Data (I2C)
C20X4 Reserved (4)
C21INTD# Interrupt D 1
C22INTB# Interrupt B 1
C23+5V +5 VDC
C24USB- Universal Serial Bus (USB)(-)
D1 AD0 Address 0
D2 AD4 Address 4
D3 C/BE0# Command, Byte Enable 0
D4 +3,3V +3.3 VDC
D5 AD12 Address 12
D6 AD15 Address 15
D7 V(I/O) +3.3 or +5 VDC
D8 LOCK# Resource Lock 1
D9 TRDY# Test Logic Ready 1
D10AD16 Address 16
D11AD20 Address 20
D12+5V +5 VDC
D13+5V +5 VDC