Science - USA (2021-12-24)

current near zero in the lower bias region and
linearly increasing in the higher bias region.
The analysis of the transistor performance
under aVSDof 0.5 V (table S1) shows that the
SS values are in the range of ~0.18 to ~1.7 V/dec,
with the shorter-channel transistors showing
greater SS than those with longer channels

(fig. S6A). TheIONcould reach ~1mA and

seemed to be less dependent on the channel

length (fig. S6B). TheION/IOFFratio reached

~10^5 for the devices with a smaller SS and

therefore more-efficient gate coupling (fig.

S6C). While the transistors fabricated in this

work showed better performance than reported

suspended transistors, the properties are not

as good as those of state-of-the-art nanotube

transistors fabricated on a substrate. The

main disadvantage is the much larger SS,

owing to the lower dielectric constant of the

vacuum gap in our devices compared with the

thin high-kdielectric film in the supported

SCIENCEscience.org 24 DECEMBER 2021¥VOL 374 ISSUE 6575 1619

Fig. 3. Room-temperature quantum interference.(A) Schematic and TEM image of a SWCNT junction with the kinks marked by arrows. (B)ISD-VGtransport
curves, showing oscillation conductance peaks at ON state. (C) Atomic model of a (22,4)/(9,4)/(22,4) junction with snapshots of the time evolution of an
electron wave packet.

Fig. 4. Chirality transition dynamics.(AtoC) NBED patterns of a CNT during
chirality transitions, with the chiral angles marked. (D) Changes of the chiral
angles revealing a converging trend toward large angles. (E) Atomic structure
of a (10,7) SWCNT with the basic vectorsb 1 andb 2 , the chiral anglec, and

misorientation angleafor a 5|8|5 defect. (F) Schematics and formation

energies (Eform) of a pair of dislocations, including the sublimation of a

carbon dimer and bond rotation steps. (G) Predicted changes of nanotube

chiral angles during chirality transitions.

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