Handbook for Sound Engineers

Consoles 977

disappear is programmed to be merely a (large) collec-

tion of serial-to-parallel data converters—no voodoo. A

slightly simplified version of it’s contents is shown in

Fig. 25-149. The FPGA takes each data line and puts it

into its own 24 bit long shift-register; when it has

counted that the necessary 24 bits have arrived, it seizes

the data and tells the mix DSP with which it is associ-

ated that the data is ready for harvesting. (A long-ago

prototype of this design actually used discrete logic shift

registers. Lots of them. It was huge. FPGAs are much

better.) To the DSP, the 32 shift register outputs are

arrayed and addressed to look exactly like memory, and

indeed, the FPGA sits on the 24 bit wide external

memory bus of the DSP, with enough address lines to

uniquely address each shift register location. Once

informed the data is ready, the DSP copies the data

values down into its own internal memory, from which

the mix code accesses it. Although this can be done in

real DSP software, it is usual to invoke a DMA routine

(direct memory access) that, depending on the sophisti-

cation of the chip, can transfer data quietly in the back-

ground of normal processing from one area or

peripheral into/out of internal memory with minimal

impact on normal operation. In practice, it always seems

to slow things up a bit (background is a relative term, it

seems), but overall, DMA is slicker. The FPGA/DSP

DMA combination does this transfer operation twice

per sample, once for left data, the other for right. These

two sets of data are held in buffers in DSP memory so

as to be in time alignment ready for the next pass of the

mix code.

25.23.2.4 Mix Code

As earlier mentioned, DSPs are designed to do some

functions really well and one of those is the FIR filter.

This involves multiplying a piece of data by a unique

coefficient, adding the product into an accumulator and

then rapidly moving on to do the whole thing all over

again (next data point, next coefficient), and again, for

as long as the filter may be. Well, from a mixing point

of view, a group output multiplies an input channel

sample by a unique coefficient, adds the product into an

accumulator, and then rapidly moves on to do the whole

thing all over again (next input sample, next coeffi-

cient), and again, until it’s done all the input channel

samples. Got it? A mixer and an FIR are as far as the

Figure 25-147. An input DSP (one of 16).

Figure 25-148. Mix stage.

Data

(^1) sdi 0
Two datalines,
four signals in pairs
SPI Control
to/from
microcontroller
2
3
sdi 1
sdo ¾
sdo 1
4
1
To mix
FPGA
inputs
2
3
4
Address
From input
convertors
Two datalines,
four signals in pairs
External
dynamic ram
(delays, etc.)
DSP
Mix FPGA Chipset
8 bit address
24 bit data bus
Mix DSP
12 outputs (6 pairs) to convertors
SPI control to/from
host microcontroller
Serial
EPROM
64 Inputs
(32 Pairs)
From input DSP:
Figure 25-149. Simplified contents of FPGA.
8 Bit shifter
Address
decoder
1 of 32
Address and chip
select from mix DSP
LSB 24 bit data bus to mix DSP MSB
Data input from
input DSP
Output enable line E
Data in
"
"
"
31
Others
"
8 Bit shifter
31
Others
"
"
"
8 Bit shifter
31
Others
"
"
"
Data in
"
Data in
"
Data in
"
SCK
1 32