DSP Technology 1173such as serial ports and timers. A DSP processor will
often have fewer peripherals, but will include a hard-
ware multiplier, often a high-speed internal memory
space, more memory addressing modes, an instruction
cache and a pipeline, and even a separation of the
program and data memory spaces to help speed program
execution. The hardware multiplier allows the DSP
processor to perform a multiplication in a single clock
cycle while microprocessors typically take multiple
clock cycles to perform this task. With clock cycles
easily exceeding 100 MHz, up to 100 million multiples
can occur every second. At this rate, 2083 multiplies
can occur in the time span required to collect one
sample of data at a 48 kHz sample rate (100 M/48,000).
A high-speed internal memory bank can be used to
speed the access to the data and/or program memory
space. By making the memory high speed, the memory
can be accessed twice within a single clock cycle,
allowing the processor to run at maximum performance.
This means that proper use of internal memory enables
more processing to take place within a given speed
processor when compared to using external memory.
The instruction cache is also used to keep the
processor running more efficiently because it stores
recently used instructions in a special place in the
processor where they can be accessed quickly, such as
when looping program instructions over signal data.
The pipeline is a sequential set of steps that allow the
processor to fetch an instruction from memory, decode
the instruction, and execute the instruction. By running
these subsystems in parallel, it is possible for the
processor to be executing one instruction while it is
decoding the next one and fetching the instruction after
that. This streamlines the execution of instructions.
31.8.1 DSP Arithmetic
Programmable DSPs offer either fixed-point or float-
ing-point arithmetic. Although floating-point proces-
sors are typically more expensive and offer less
performance than fixed-point processors, VLSI hard-
ware advances are minimizing the differences. The
main advantage of a floating-point processor is the abil-
ity to be free of numerical scaling issues, simplifying
the algorithm development and implementation process.
Most people naturally think in terms of fractions and
decimal points, which are examples of floating-point
numbers. Typically, floating-point DSPs can represent
very large and very small numbers and use 32-bit (or
longer) words composed of a 24-bit mantissa and an
8-bit exponent, which together provide a dynamic range
from 2^127 to 2^128. This vast range in floating-point
devices means that the system developer does not need
to spend much time worrying about numerical issues
such as overflow (a number too large to be represented)
or underflow (a number too small to be represented). In
a complicated system, there is enough to worry about
without having to worry about numerical issues as well.
Fixed-point arithmetic is called fixed-point because
it has a fixed decimal point position and because the
numbers have an implicit scale, depending on the range
that must be represented. This scale must be tracked by
the programmer when performing arithmetic on
fixed-point numbers. Most DSPs use the fixed-point
2s-complement format, in which a positive number is
represented as a simple binary value and a negative
value is represented by inverting all the bits of the
corresponding positive value and then adding 1.
Assuming a 16-bit word, there are 2^16 = 65,536 possible
combinations or values that can be represented which
allows the representation of numbers ranging from the
largest positive number of 2^15 1 = 32,767 to the
smallest negative (e.g., most negative) number of
215 =32,768.
There are many times when it is important to repre-
sent fractions in addition to integer numbers. To repre-
sent fractions, the implied position of the decimal point
must be moved. When using 16-bit arithmetic to repre-
sent fractions only, with no integer component, a Q15
arithmetic format with an implied decimal point and 15
bits of fraction data to the right of the decimal point
could be used. In this case, the largest number that can
be represented is still 2^15 1, but now this number
represents 32,767/32,768 = 0.999969482, and the
smallest negative number is still 215 , but this number
represents –32,768/32,768 = –1. Using Q15 arithmetic,
it is possible to represent numbers between
0.999969482 and –1. As another example, representing
numbers that range between 16 and –16 would require
Q11 arithmetic (4 bits before the implied decimal
point). An implementation may use different implied
decimal positions for different variables in a system.
Because of the smaller word size and simpler arith-
metic operations when compared to floating-point
processors, fixed-point DSPs typically use less silicon
area than their floating-point counterparts, which trans-
lates into lower prices and less power consumption. The
trade-off is that, due to the limited dynamic range and
the rules of fixed-point arithmetic, an algorithm
designer must play a more active role in the develop-
ment of a fixed-point DSP system. The designer has to
decide whether the given word width (typically 16 or 24
bits) will be interpreted as integers or fractions, apply
scale factors if required, and protect against possible