Handbook for Sound Engineers

852 Chapter 25

connected back to back to form close to ideal bidirec-
tional analog transmission gates, are manufactured in all
manner of variations and packages by IC manufacturers.
At extremes of performance minor control-port break-
through (charge injection) can rear its head and be taken
into consideration.
Early versions of CMOS transmission gates had
some rather untoward vices. They were raw CMOS
elements, and one of their main attributes, the extremely
high impedances in their off states and of their control
ports, made them liable to destruction by normal
amounts of static electricity. Also, they tended to latch
up easily if any of the MOS junctions inadvertently got
reverse biased into conduction (this happened easily if
the signal voltage passing through a gate even momen-
tarily exceeded the supply voltage). Most present
devices are now gate protected to prevent static blatting,
and the worst that happens with the audio signal
exceeding the switch supply voltage by a small amount
is that the switch breaks over (i.e., conducts audio
momentarily). It does not result in the fatal conse-
quences it once did.

Perhaps the best-known and most-used switch of this
kind is the 4016 (and its younger brother the 4066,
which is essentially identical but for a lower on resis-
tance). It is a 14-pin dual package containing four inde-
pendently controllable CMOS transmission gates. Each
gate can pass up to the IC’s supply voltage (typically
18 Vdc) into a load exceeding 10 k: with a distortion
of about 0.4% in rudimentary switching formats. Obvi-
ously, both the distortion figure and the head room
availability of 18 dB above 0.775 V (for an 18 Vdc
supply) are both woefully inadequate by today’s
expected console standards. Another less obvious pitfall
is the decreasing switch isolation at high frequencies
due to leakage capacitance across the gate.
Fig. 25-31A gives a typical representation of the vari-
ation of the on resistance of a CMOS transmission gate
with signal voltage applied to the gate. This variation in
resistance is, of course, the source of the distortion. If we
could restrict the signal voltage to within that (linear) bit
in the middle, or better still virtually eliminate the signal
voltage altogether, our problem would go away.
Placing the switching element right up against a
virtual-earth ground point, as in Fig. 25-32A, achieves
this signal voltage elimination; the switch now behaves
as a two-state resistor. When closed, the on resistance
variation, which will be small anyway because of the
very low voltage swing across it, will be effectively
swamped by the (relatively) much larger series resis-
tance. When open, the off resistance extends the total
series resistance to a value approaching infinity. In prac-

tice, the on-off ratio is not really adequate. Capacitance

across printed circuit tracks and in the device encapsula-

tion itself, combined with common-ground current and

other essentially flat-response crosstalk mechanisms,

results in a cross-switch leakage characteristic ulti-

mately rising 6 dB/octave against frequency. Also,

despite the fact that the distortion problem is now

largely resolved, there still remains a head room

problem when the switch is open. If the source voltage

presented to the series resistor exceeds that of the power

supply of the CMOS gates, the gate will break over,

turning on for that excessive portion of the input wave-

form.

Attenuating the source signal by the needed amount

before it hits the gate skirts this hangup. Unfortunately,

this worsens the noise gain of the virtual-ground ampli-

fier by the amount of that attenuation. In Fig. 25-32B

dropping an equal-value resistor to the series resistor to

ground from its junction with the gate is a working

approach. The maximum signal that can be present

across the gate when off is now half that previously,

which is usually more than enough attenuation to

prevent breakover. This 6 dB loss is magically made up

for in the on mode because the source resistance of the

signal into the amplifier is now halved (series resistance

effectively in parallel with the dropped resistor).

Incidentally, the crosstalk improves as a conse-

quence by almost 6 dB—less signal voltage actually

within the chip. For many practical purposes, this

switching configuration, with its performance limita-

tions as defined, is quite adequate. For instance, the

Figure 25-31. Typical CMOS transmission gate linearity.

+30%

+20%

+10%

0%

10V 5 0 +5 +0

Device limits

Percentage

channel

resistance

change Device limits

Signal voltage

+20

+10

Percentage

channel

resistance

change

10 20 30 40 50 60

Channel current–mA

B. Channel resistance variation with through current.

A. With signal voltage applied to the gate.

(Bang)