Consoles 85525.9.9 Processor Control
The seemingly great mass of logic circuitry enclosed in
the dotted lines allows the card to be controlled by a
computer or microcontroller’s I/O lines (depending on
the scale of the system). Very little additional decoding
is necessary to allow this interface to hang straight onto
a CPU bus. It’s really just six flip-flops acting as
memory elements (so that the card can remember what
the CPU has told it to do) and six tristate buffers that, on
request, tell the CPU what the card is actually doing.
This memory both saves the CPU from having to store
the matrix routing information somewhere else and also
acts as a very useful diagnostic aid to help find out what
isn’t doing what, where, and why.
For ordinary direct operation, this logic can be left
off the card completely and linked across (between the
Xs on the diagram). The NAND gates in the top
left-hand corner merely organize the CPU bus informa-
tion to fire the appropriate clock, enables, and resets to
the memory elements.
CMOS 4000 series logic operating at 5 Vdc is not
the fastest logic family in existence and is too slow for
most microprocessor CMOS to drive directly. The
circuitry shown here will operate successfully from a
microcontroller running at a MHz or two, which is very
slow in the computer world. This slowness is not a
problem in reality, since the practical way of dealing
with this is to hang the entire switching matrix logic
system off a bunch of the CPU input/output ports,
masquerading as a local address/data/control bus system
at a fairly leisurely software-controlled rate.
A convenient 16 input-output (I/O) line is required
(two lots of eight, handy for PCs). A single 8255 or
6850 Peripheral Interface Adapter (PIA) would handle
this matrix. Being software controlled, the I/O lines may
be timed a little more gently than the hardware-deter-
mined processor buses.
A separate address decoder card however takes
many of the card address bits that are required (5 for 32,
6 for 64, 7 for 128) and generates the decoded feeds for
the card enable (CE) on each matrix card. This is very
simply accomplished with a daisy chain of 4028
binary-to-decimal decoders, Fig. 25-34.
This slow interface has the single benefit that it is
fully featured; it is common with faster and more
capable processors with plenty of cheap memory aboard
to not require the readback facility; nearly all the inter-
face logic can be replaced by parallel bus latches such
as HC373s with suitable address decoding. HC of
course will operate at reasonably high clock rates, even
directly off a processor’s data buses. FPGAs, the ulti-
mate octopus of peripheral handling, can handily absorb
all the described interfacing.25.9.10 Audio PathIn the bottom left-hand corner of Fig. 25-33 is an analog
mix-amp and line amp, which are the group output
stages for the channel to which the particular matrix
card is relevant and they are as close as they can get to
the buses.
The mix-bus input is tied on the back of the edge
connector in the card frame to the bus it is responsible
for sensing. This ensures card replaceability and redun-
dancy; individually doctored cards are the kiss of death
from a maintenance standpoint since there is no means
of getting a given path going again (in the event of a
failure) without actually fixing the fault. The old
standby of swapping cards wouldn’t work; it is always
best to keep individualism off the cards.
Note that no values are attributed to the feedback
capacitor around the mix-amp, since this not only has to
compensate for the amplifier’s own tendency to insta-
bility but for the added irritation to this of the bus
impedance—an unknown until actual construction. Also
note a capacitor across part of the switcher input series
resistance. This provides a variable high-frequency
kick, which can be of assistance in sorting out
frequency and phase response quirks in problematic bus
systems. This is, fortunately, very rarely needed and is
provided just in case.
Fig. 25-35 shows the audio path through the
switcher, devoid of frills. The 1 k: resistor RS, which
does not appear in Fig. 25-35, is internal to the HI506A,
appearing on each of the switch inputs. Although a
minor nuisance in this application, which means the
CMOS switches are not actually switching a zero
impedance, they are part of the device’s internal protec-
tion against, principally, static electricity damage—a
worthwhile sacrifice.
The total source impedance before the bus is about
9.9 k: , which with the addition of the 100: buffering
resistor becomes 10 k: before the virtual-earth input of
the mix-amp. A 4.7 k: gain-trim preset in series with
8.2 k: gives a gain determining feedback resistor swing
of approximately 8.2–12.9 k: , which corresponds to a
swing of 1.7 dB to +2.2 dB.
The line amp is a simple beefed-up inverting ampli-
fier necessary to maintain the absolute input-output
phase relationship.