Handbook for Sound Engineers

Consoles 957

required. There is but one comparator unlike in flash,

easing accuracy. Conversion takes at least as many

cycles as there are bits of resolution. Operation consists

of comparing internal voltages, weighted in accordance

with the bit value, against a frozen (by a sample and

hold circuit) sample of the input signal. It needs to be

frozen since the conversion is not instantaneous and the

input signal level could change in the time it does take.

The most significant bit’s value is half the permissible

input range, the second a quarter, the third an eighth, the

fourth a sixteenth, and so on in binary weighting. They

are applied in turn to the comparator, MSB first. If the

sample is larger than the MSB, then the MSB is left

asserted; if not, it is dropped. The next weight is

applied; if the input sample is still larger than the

combination of MSB and No. 2, then No. 2 is left

asserted, and so on. Eventually all the bits are tried

against the input sample with the bits remaining

asserted, forming the 1s of the digital word, the

remainder the 0s.

Both of the above converters generate an absolute

digital value of the input signal at each sample period.

Sigma-Delta Conversion. Sigma-delta, or also called
delta-sigma, conversion starts off in essence by
measuring relatively how far the input signal moves, up
or down, rather than stating exactly where it is. Conver-
sion occurs much more often than the required output
sampling rate (e.g., 48 kHz) often 128 or 256 times
higher. The conversion itself is much simpler though.
Simplistically, at each conversion it only has to make the
decision whether the input signal has moved up or down
from where it was last sampled. Its output is a very fast
stream of up and down signals; the sampling is fast
enough that it can keep pace with the input signal’s prob-
able changes, sensing automatically whether large level
shifts or tiny ones are taking place. Subsequent intelli-
gence (filtering) keeps track of this torrent of single-bit
state changes and renders down a conventional digital
word for an absolute output value.
As a method it has many advantages, not the least of
which being the enormous internal sampling rate; the
antialiasing filter can be relaxed considerably, both in
order and cutoff frequency (often it just consists of a
single- or double-order filter set much higher in
frequency than with other encoders—and sometimes
left out completely!). Filtering is left to within the
digital domain.
They are also monotonic, having none of the prob-
lems of the other types of comparator level or ladder
accuracy. What they do have, and which can be a
concern in some applications, is a comparatively very

long latency (signal processing delay time) before a

relevant sample pops out for digital digestion; at normal

sample rates and depending on the length of the FIR

decimation filters within, this latency can be around a

millisecond or so. Sigma-delta A/Ds predominate in

pro-audio.

25.18.2 Digital-to-Analog Conversion (DAC)

25.18.2.1 Conventional Ladder DACs

A means of turning the processed output signal from the

DSP back into analog is necessary. These are described

in Chapters 31, 38, and 39, but for completeness are

outlined here. A DAC adds together voltages (or

currents) of weightings corresponding to the importance

of the binary bits. Fig. 25-127 shows a simplistic DAC.

The required output digital word is applied and the most

significant bit, if set high, sources a current of 1 mA.

The next most significant bit sources half that or

0.5 mA, the next bit half that (0.25 mA), and so on

down to 7.8μA increment for the least significant bit. In

the 8 bit converter shown, the maximum output current

is just short of 2 mA (1.996 mA) with all the bits set

(one extreme) and none if all are low (the other

extreme). Any current between those two, in 255 steps,

which is the resolution of an 8 bit word, can be achieved

by setting up a permutation of the input bits. This output

current can be converted to an output voltage by a

summing amplifier.

There are other kinds of D/A techniques, probably

the most common being the R/2R ladder, Fig. 25-128.

Figure 25-127. Simplistic digital to analog converter.

Digital weighting

Most

significant

bit

Least

significant

bit

1 mA

0.5 mA

0.25 mA

125 MA

62.5 MA

31.25 MA

15.6 MA

7.8 MA

0

 2 mA

1 k 7

0 to

2 V