968 Chapter 25
seen clearly; the b0 and b2 coefficients are really quite
small; the reciprocal of this value is the amount of gain
being generated in the IIR output chain. Thankfully,
commercial design packages and most cookbook coeffi-
cient calculation routines take this scaling into account.
But the underlying issue is quite serious. Using, say,
0.0001 as a b0 coefficient (not unrealistic) and assuming
a maximum input signal of 1 (the maximum signal range
using the fractional arithmetic scheme in some
fixed-point DSPs is 1 to 1), then a value of 0.0001 will
end up in the accumulator, and despite the huge feedack-
derived gain in the IIR output chain, the contribution to
the output from the input signal is still only 0.0001; this
corresponds to 80 dB. If the output were to be trun-
cated to 24 bits (144 dB) the bottom 13 or so bits worth
of the input signal would effectively, be sawn off and
thrown away, leaving us with an 11-bit system. In
numbers, this leaves a maximum signal to floor ratio of
only 64 dB; if the normal operating level of the system
is 20 dBFS (deciBels below Full Scale) (0.1), that is
only 44 dB signal to floor. Practically, with rounding,
noise shaping , or dithering, things are worse.
The good news is that such quantization noise in
filters can sometimes be masked somewhat by the very
signals the filter is passing; the bad news is that when it
is audible, it is Audible. And even when not overtly
audible, it lends itself to a disquieting roughness to the
sound that is difficult to pin down. The accumulator has
all the width needed for valid data; standard practice on
any filter on which this is even likely to be an issue is to
make the IIR chain delay storage wide enough to fully
encompass the attenuated input signals. In the specific
example of a 24 bit fixed-point processor, the IIR output
delay chain is made long, or double width at 48 bits. It
also means that nearly always the a1 and a 2 IIR multi-
plies need to be long too—i.e. the lower 24 bits need to
be MAC’ed in with the upper 24, which increases
execution time of the filter.
Sharc and other floater programmers are permitted to
smile at this point. It is a happy day to doff the shackles
of fixed point.25.21.2.5 Cascaded BiquadsHaving previously noted that IIR filters with more than
a biquad’s worth of delays and multiplies are not attrac-
tive, there are approaches to coupling more than one
biquad with the intention of making more complex or
effective filters or simply those of a higher order. Better
than just running one after another. Fig. 25-138 shows
such an arrangement; the second biquad uses the output
delays of the first as its input delays, and so on.25.21.3 Parametric EQRaw biquads can take care of most traditional filtering.
One approach to doing a console-style parametric EQ
section, with independent control over center frequency
and Q of the employed filter and of the amount of lift or
cut introduced, is shown in Fig. 25-139. A standard
biquad is fed directly from the source audio, which is
also attenuated by (in this case) 12 dB by the expedient
of arithmetically shifting the data two bits to the right
(down), or by multiplying by 0.25, in the DSP. The
filter’s output, fed through an attenuator, is summed
with the attenuated direct signal, and the result arithmet-
ically shifted (ASL) two bits to the left (up 12 dB). This
shifting up and down allows a correspondingly higher
amount of the filter to be present in the output, which is
required if high levels of boost are required. This
example’s 12 dB allows a maximum boost of 13.8 dB to
be achieved, which happily encompasses the ±12 dB
control range often found in EQs; more boost capa-
bility would require greater shifting down and back up.
One can in a floater (floating-point DSP) leave the
straight signal alone and simply multiply the filterFigure 25-137. 3 point FIR filters from b0, b1, and b2 of Fig.
25-136.
0dB
Alt
100
dc
A.Fs/20dB
Alt
100
dc
B.Fs/20dB
Alt
100
dc
C.Fs/2