Reverse Engineering for Beginners

CHAPTER 17. FLOATING-POINT UNIT CHAPTER 17. FLOATING-POINT UNIT

VDIV,VMULandVADD, are instruction for processing floating point numbers that computequotient,productand sum,

respectively.

The code for Thumb-2 is same.

17.5.3 ARM: Optimizing Keil 6/2013 (Thumb mode)

f

PUSH {R3-R7,LR}

MOVS R7, R2

MOVS R4, R3

MOVS R5, R0

MOVS R6, R1

LDR R2, =0x66666666 ; 4.1

LDR R3, =0x40106666

MOVS R0, R7

MOVS R1, R4

BL __aeabi_dmul

MOVS R7, R0

MOVS R4, R1

LDR R2, =0x51EB851F ; 3.14

LDR R3, =0x40091EB8

MOVS R0, R5

MOVS R1, R6

BL __aeabi_ddiv

MOVS R2, R7

MOVS R3, R4

BL __aeabi_dadd

POP {R3-R7,PC}

; 4.1 in IEEE 754 form:

dword_364 DCD 0x66666666 ; DATA XREF: f+A

dword_368 DCD 0x40106666 ; DATA XREF: f+C

; 3.14 in IEEE 754 form:

dword_36C DCD 0x51EB851F ; DATA XREF: f+1A

dword_370 DCD 0x40091EB8 ; DATA XREF: f+1C

Keil generated code for a processor without FPU or NEON support. The double-precision floating-point numbers are
passed via generic R-registers, and instead of FPU-instructions, service library functions are called (likeaeabi_dmul,
__aeabi_ddiv,aeabi_dadd) which emulate multiplication, division and addition for floating-point numbers. Of
course, that is slower than FPU-coprocessor, but still better than nothing.

By the way, similar FPU-emulating libraries were very popular in the x86 world when coprocessors were rare and expensive,

and were installed only on expensive computers.

The FPU-coprocessor emulation is calledsoft floatorarmel(emulation) in the ARM world, while using the coprocessor’s

FPU-instructions is calledhard floatorarmhf.

17.5.4 ARM64: Optimizing GCC (Linaro) 4.9

Very compact code:

Listing 17.4: Optimizing GCC (Linaro) 4.9

f:

; D0 = a, D1 = b

ldr d2, .LC25 ; 3.14

; D2 = 3.14

fdiv d0, d0, d2

; D0 = D0/D2 = a/3.14

ldr d2, .LC26 ; 4.1

; D2 = 4.1

fmadd d0, d1, d2, d0

; D0 = D1*D2+D0 = b*4.1+a/3.14

ret

; constants in IEEE 754 format:

.LC25: