CHAPTER 19. MANIPULATING SPECIFIC BIT(S) CHAPTER 19. MANIPULATING SPECIFIC BIT(S)
19.4.3 MIPS.
GCC 4.4.5 for MIPS does mostly the same:
Listing 19.23: Optimizing GCC 4.4.5 (IDA)my_abs:
; move from coprocessor 1:
mfc1 $v1, $f12
li $v0, 0x7FFFFFFF
; $v0=0x7FFFFFFF
; do AND:
and $v0, $v1
; move to coprocessor 1:
mtc1 $v0, $f0
; return
jr $ra
or $at, $zero ; branch delay slot
set_sign:
; move from coprocessor 1:
mfc1 $v0, $f12
lui $v1, 0x8000
; $v1=0x80000000
; do OR:
or $v0, $v1, $v0
; move to coprocessor 1:
mtc1 $v0, $f0
; return
jr $ra
or $at, $zero ; branch delay slot
negate:
; move from coprocessor 1:
mfc1 $v0, $f12
lui $v1, 0x8000
; $v1=0x80000000
; do XOR:
xor $v0, $v1, $v0
; move to coprocessor 1:
mtc1 $v0, $f0
; return
jr $ra
or $at, $zero ; branch delay slot
One singleLUIinstruction is used to load 0x80000000 into a register, becauseLUIis clearing the low 16 bits and these
are zeroes in the constant, so oneLUIwithout subsequentORIis enough.
19.4.4 ARM.
Optimizing Keil 6/2013 (ARM mode)
Listing 19.24: Optimizing Keil 6/2013 (ARM mode)my_abs PROC
; clear bit:
BIC r0,r0,#0x80000000
BX lr
ENDP
set_sign PROC
; do OR:
ORR r0,r0,#0x80000000
BX lr
ENDP
negate PROC
; do XOR:
EOR r0,r0,#0x80000000