CHAPTER 45. BRANCHLESS ABS() FUNCTION CHAPTER 45. BRANCHLESS ABS() FUNCTION
45.2 Optimizing GCC 4.9 ARM64
GCC 4.9 for ARM64 generates mostly the same, just decides to use the full 64-bit registers. There are less instructions,
because the input value can be shifted using a suffixed instruction (“asr”) instead of using a separate instruction.
Listing 45.2: Optimizing GCC 4.9 ARM64my_abs:
; sign-extend input 32-bit value to X0 64-bit register:
sxtw x0, w0
eor x1, x0, x0, asr 63
; X1=X0^(X0>>63) (shift is arithmetical)
sub x0, x1, x0, asr 63
; X0=X1-(X0>>63)=X0^(X0>>63)-(X0>>63) (all shifts are arithmetical)
ret