APPENDIX B. ARM APPENDIX B. ARM
- X31—register always contains zeroAKAXZR or “Zero Register”. It’s 32-bit part is called WZR.
- SP, not a general purpose register anymore.
See also: [ARM13c].
The 32-bit part of each X-register is also accessible via W-registers (W0, W1, etc).
High 32-bit part low 32-bit part
X0
W0B.5 Instructions
There is a-Ssuffix for some instructions in ARM, indicating that the instruction sets the flags according to the result. In-
structions which lacks this suffix are not modify flags. For exampleADDunlikeADDS will add two numbers, but the flags
will not be touched. Such instructions are convenient to use betweenCMPwhere the flags are set and, e.g. conditional
jumps, where the flags are used. They are also better in terms of data dependency analysis (because less number of registers
are modified during execution).
B.5.1 Conditional codes table.
Code Description Flags
EQ Equal Z == 1
NE Not equal Z == 0
CSAKAHS (Higher or Same) Carry set / Unsigned, Greater than, equal C == 1
CCAKALO (LOwer) Carry clear / Unsigned, Less than C == 0
MI Minus, negative / Less than N == 1
PL Plus, positive or zero / Greater than, equal N == 0
VS Overflow V == 1
VC No overflow V == 0
HI Unsigned higher / Greater than C == 1 and Z == 0
LS Unsigned lower or same / Less than or equal C == 0 or Z == 1
GE Signed greater than or equal / Greater than or equal N == V
LT Signed less than / Less than N != V
GT Signed greater than / Greater than Z == 0 and N == V
LE Signed less than or equal / Less than, equal Z == 1 or N != V
None / AL Always Any