Preamplifi ers and Input Signals 203illustrated in Figure 7.21 , where even at currents in the 1- to 10-mA region, dynamic
impedances of the order of 100 kilohms may be expected.
A typical circuit layout that utilizes this characteristic is shown in Figure 7.33 , in which
R 1 and R 2 form a potential divider to defi ne the base potential of Q 1 , and R 3 defi nes the
total emitter or collector currents for this effective base potential.
This confi guration can be employed with transistors of either PNP or NPN types, which
allow the circuit designer considerable freedom in their application.
An improved, two-transistor, constant current source is shown in Figure 7.34. In this, R 1
is used to biasQ 2 into conduction, and Q 1 is employed to sense the voltage developed
acrossR 2 , which is proportional to emitter current, and to withdraw the forward bias from
Q 2 when that current level is reached at which the potential developed across R 2 is just
suffi cient to cause Q 1 to conduct.
The performance of this circuit is greatly superior to that of Figure 7.33 in that the output
impedance is about 10 greater and the circuit is insensitive to the potential, Vref. ,
applied toR 1 , so long as it is adequate to force both Q 2 and Q 1 into conduction.
An even simpler circuit confi guration makes use of the inherent very high output
impedance of a junction FET under constant gate bias conditions. This employs the
circuit layout shown in Figure 7.35 , which allows a true “ two-terminal ” constant current
R 1Q 1R (^2) R
3
0V
Vref Icoutput
Figure 7.33 : Transistor constant current source.