Audio Engineering

298 Chapter 9

layout, coupled with the high stage gain of the BJT. The source potential of the JFET
(Q 2 ) will be determined by the reverse bias appearing across the source/gate junction,
and could typically be of the order of 2–5 V, which will defi ne the collector potential
applied toQ 1. A further common application of this type of layout is that in which the
cascode FET ( Q 2 in Figure 9.15 ) is replaced by a high-voltage BJT. The purpose of this

0V 0V

Output

R 3

R 4

R 2

Q 1

Q 2

C 1

R 1

C 2

Input

Vcc

Figure 9.14 : Bipolar/FET cascode.

0V 0V

Output

R 2

R 3

Q 1

Q 2

C 1

R 1

C 2

Input

Vcc

Figure 9.15 : FET/FET cascode.