Audio Engineering

Digital Audio Fundamentals 421

Figure 14.8 : In (a) two convertors are joined by a serial link. Although simple, this system
is defi cient because it has no means to prevent noise on the clock lines causing jitter at the
receiver. In (b) a phase-locked loop is incorporated, which fi lters jitter from the clock.

Clock

Clock

ADC Parallel Data DAC

to

serial

Noise

Serial

to

parallel

Noise on data

is rejected

Analog

out

Analog

in

Clock jitter

due to noise

isnot

rejected

(a)

Clock

ADC Parallel Data DAC

to

serial

Noise

Serial

to

parallel

Noise on data

is rejected

Analog

in

Analog

out

Jitter-free

clock

Phase-

locked

loop

(b)