Audio Engineering

444 Chapter 15

logic that has no timing or memory associated with it: for such systems other techniques,
such as state machine analysis, are better used instead.

The simplest arrangement of gates that exhibit memory, at least while power is still
applied, is the cross-coupled NAND (or NOR) gate ( Figure 15.4 ). More complex

AND AB C

Inputs

0

0

1

1

0

1

0

1

0

0

0

1

AB C

A

0

0

1

1

0

1

0

1

0

1

1

0

0

1

1

1

BC

A

0

0

1

1

0

1

0

1

1

1

1

0

BC

AB C

C  A. B

C  AB

A

0

1

0

1

0

0

1

1

1

0

0

0

BC

A

0

1

0

1

0

0

1

1

0

1

1

0

BC

Name Symbol Truth table Logic equation

Outputs

OR

NOT

NAND

A

A

A A

A

B B A B A A B

B

NOR

EXOR

1

1

B

Q C

C

CC

C

C

C

C

&

&

1

&

C  A

i

C  A. B

C  AB

C  AB

 ABAB

Figure 15.3 : Symbols and truth tables for the common basic gates. For larger arrays of gates

it is more useful to express the overall logical function as a set of sums (the OR function)

and products (the AND function); this is the terminology used by gate array designers.