Audio Engineering

Representation of Audio Signals 447

Serial data

input

Parallel

load

Clock

pulses

D Q

Po P Pn

D Q D Q D Q

Parallel data inputs

Serial

output

(b)

Figure 15.5(b) : This arrangement of FFs produces the shift register. In this circuit, a pattern

of Is and 0 s can be loaded into a register (the load pulses) and then can be shifted out

serially one bit at a time at a rate determined by the serial clock pulse. This is an example of

a parallel in serial out (PISO) register. Other varieties include LIFO (last in fi rst out), SIPO

(serial in parallel out), and FILO (fi rst in last out). The diagrams assume that unused inputs

are tied to ground or to the positive supply rail as needed.

polarity of a magnetic fi eld, state of waveform phase, and direction of an electric current.
The most common voltage levels referred to are those used in the common 74 00 logic
families and are often referred to as TTL levels. A logic 0 (or low) will be any voltage
that is between 0 and 0.8 V while a logic 1 (or high) will be any voltage between 2.0 V
and the supply rail voltage, which will be typically 5.0 V. In the gap between 0.8 and
2.0 V the performance of a logic element or circuit is not reliably determinable as it is in
this region where the threshold between low and high logic levels is located. Assuming
that the logic elements are being used correctly, the worst-case output levels of the TTL
families for a logic 0 is between 0 and 0.5 V and for a logic 1 is between 2.4 V and the
supply voltage. The difference between the range of acceptable input voltages for a
particular logic level and the range of outputs for the same level gives the noise margin.
Thus for TTL families, the noise margin is typically in the region of 0.4 V for both logic
low and logic high. Signals whose logic levels lie outside these margins may cause