Audio Engineering

Representation of Audio Signals 449

Bit

Clock

68

0110 1000

h

65

0110 0101

e

6L

0110 1101

l

6C

0110 1101

l

6F

0110 1111

o

Hex

Binary

ASCII

0 1 2 3 4 5 6 7

(a)

Figure 15.6(a) : Parallel transmission: a data strobe line DST (the—sign means active low)

would accompany the bit pattern to clock the logic state of each data line on its falling edge

and is timed to occur some time after the data signals have been set so that any refl ections,

cross talk, or skew in the timing of the individual data lines will have had time to settle. After

theDST signal has returned to the high state, the data lines are reset to 0 (usually they

would only be changed if data in the next byte required a change).

parallel interface. Achieving this higher data rate requires that the sending and receiving
impedances are accurately matched to the impedance of the connecting cable. Failure to
do this will result in signal refl ections, which in turn will result in received data being
in error. This point is of practical importance because the primary means of conveying
digital audio signals between equipments is by the serial AES/EBU signal interface at a
data rate approximately equal to 3 Mbits per second.