462 Chapter 15
The process of shifting and adding could be programmed in a series of program steps
and executed by a microprocessor but this would take too long. Fast multipliers work
by arranging that all of the available shifted combinations of one of the input numbers
are made available to a large array of adders, while the other input number is used to
determine which of the shifted combinations will be added to make the fi nal sum.
The resulting word width of a multiplication equals the sum of both input word widths.
Further, we will need to recognize where the binary point is intended to be and arrange
to shift the output word appropriately. Quite naturally the surrounding logic circuitry will
have been designed to accommodate a restricted word width. Repeated multiplication
must force the output word width to be limited. However, limiting the word width
has a direct impact on the accuracy of the fi nal result of the arithmetic operation. This
curtailment of accuracy is cumulative since subsequent arithmetic operations can have no
knowledge that the numbers being processed have been “ damaged. ”
Two techniques are important in minimizing the “ damage. ” The fi rst requires us to maintain
the intermediate stages of any arithmetic operation at as high an accuracy as possible for
as long as possible. Thus although most conversion from analogue audio to digital (and the
converse digital signal conversion to an analogue audio signal) takes place using 16 bits,
the intervening arithmetic operations will usually involve a minimum of 24 bits.
Decimal Binary
00000
00011
00000
00000
000001111
and another example:
12 01100
13 01101
156 010011100