Audio Engineering

Representation of Audio Signals 483

A very simple form of DAC is based on switching currents into a virtual earth summing
point. The currents are derived from a R–2R ladder, which produces binary weighted
currents ( Figure 15.25 ). The incoming binary data directly controls a solid state switch,
which routes a current either into the virtual earth summing point of the output amplifi er
or into the local analogue ground. Since the voltage across each of the successive

Sampled input

signal

Comparator Clock SAR Conversion completed

Paralled

output

data

 DAC



Clock pulse conversion periods

T 2 T 3 T 4 T 5 T

DAC O/P

too low

using only

MSB

0

DAC output value

1

2

3

4

5

6

7

DAC output

too low

Input signal to be quantised

DAC O/P

too high

Nearest output

value attained

by PAC

Figure 15.24 : The SAR operates with a DAC and a comparator, initially reset to zero.

At the fi rst clock period the MSB is set and the resulting output of the DAC is compared to

the input level. In the example given here the input level is greater than this and so the MSB

value is retained and, at the next clock period, the next MSB is set. In this example

the comparator output indicates that the DAC output is too high, the bit is set to 0, and

the next lower bit is set. This is carried out until all of the DAC bits have been tried.

Thus a 16-bit ADC would require only 17 clock periods (one is needed for reset)

in which to carry out a conversion.