Audio Engineering

Compact Disc 521

words. Correcting random errors is easier so the procedure used in the Reed–Solomon
code endeavors to break down burst errors into groups of scattered random errors.
However, it greatly facilitates remedial action if the presence and location of the error can
be detected and “ fl agged ” by some added symbol.

Although the existence of an erroneous bit in an input word can sometimes be detected
merely by noting a wrong word length, the basic method of detecting an error in received
words is by the use of “ parity bits. ” In its simplest form, this would be done by adding
an additional bit to the word sequence, as shown in Figure 16.17(a) , so that the total
(using the logic rules shown in Figure 16.17 ) always added up to zero (a method known
as “ even parity ” ). If this addition had been made to all incoming words, the presence of
a word plus parity bit that did not add up to ‘ 0 ’ could be detected instantly by a simple
computer algorithm and it could then be rejected or modifi ed.

16.4.2 Faulty Bit/Word Replacement

Although the procedure shown earlier would alert the decoder to the fact that the word
was in error, the method could not distinguish between an incorrect word and an incorrect
parity bit—or even detect a word containing two separate errors, although this might be
a rare event. However, the addition of extra parity bits can indeed correct such errors as
well as detect them, and a way by which this could be done is shown in Figure 16.17(b).
If a group of four 4-bit input words, as shown in lines a–d, each has a parity bit attached
to it, as shown in column q, so that each line has an even parity, and if each column has a
parity bit attached to it, for the same purpose, as shown in line e, then an error, as shown
in grid reference (b.n) in Figure 16.17(c) , could not only be detected and localized as
occurring at the intersection of row b and column n, but it could also be corrected, since
if the received value ‘ 0 ’ is wrong, the correct alternative must be ‘ 1 ’.

Figure 16.17 : Parity bit error correction. Logic: 0  0  0, 0  1  1, 1  1  0.

1 1 0 1 1

Word

Parity bit

(a)

1 1 0 1 1

mnop q

0 1 0 1 0

1 0 1 1 1

0 1 1 0 0

0

a

b

c

d

e1 0 1 0

(b)

1 1 0 1 1

0 0 0 1 0

1 0 1 1 1

0 1 1 0 0

0 1 0 1 0

(c)

1 1 0 1 1

0 1 0 1 1

1 0 1 1 1

0 1 1 0 0

0 1 0 1 0

(d)