Audio Engineering

Digital Audio Production 607

code generator may be taken in serial form (from any of the data-latch outputs) or in
parallel form (from all the data latch outputs). In operation, imagine that the output of
stage B starts with a 1 as power is applied, but that all the other outputs start with a 0.
Note that the output of the XOR gate will only equal 1 when its inputs are of a different
state (i.e., nonidentical). We can now predict the ensuing pattern that results as the shift
register is clocked:

2

3

4 U1A

ABCD

74LS74 74LS74 74LS74

74LS86

6

1

512

(^10)
(^13)
U1B U2A
U3A
(^321)
9 4
1
25
6
3
8
11
74LS74
12
(^10)
(^13)
U2B
Bit serial
pseudo-random
data
Clock
input
Bit parallel pseudo-random data
9
8
Q 11
Q
P
CL
DR
CLK
Q
Q
P
CL
DR
CLK
Q
Q
P
CL
DR
CLK
Q
Q
P
CL
DR
CLK
Figure 20.6 : Chain-code generator.
State Output (A,B,C,D)
0 (initial) 0,1,0,0
1 0,0,1,0
2 1,0,0,1
3 1,1,0,0
4 0,1,1,0
5 1,0,1,1
6 0,1,0,1
7 1,01,0
(Continued)