Video Synchronization 831relatively long distances using the same coaxial cable as used for analogue video signals.
This makes its adoption and implementation as simple as possible for existing television
facilities converting from analogue to digital video standards.
28.8.3 Serial Digital Video Interface
SMPTE 259M specifi es the parameters of the serial digital standard. This document
specifi es that parallel data in the format given in the previous section be serialized and
transmitted at a rate 10 times the parallel clock frequency. For component signals, this is
27 Mbits/s 10 270 Mbits/s.Serialized data must have a peak-to-peak amplitude of 800 m V ( 10%) across 75 Ω , have
a nominal rise time of 1 ns, and have a jitter performance of 250 ps. At the receiving
end, signals must be converted back to parallel in order to present original parallel data to
the internal video processing. (Note that no equipment processes video in its serial form,
although digital routing switchers and DAs, where there is no necessity to alter the signal,
only buffer it or route it, do not decode the serial bit stream.)
Serialization is achieved by means of a system illustrated in Figure 28.11. Parallel data
and a parallel clock are fed into input latches and then to a parallel to serial conversion
circuit. The parallel clock is also fed to a phase-locked loop, which performs parallel
clock multiplication (by 10 times). A sync detector looks for TRS information and
ensures that this is encoded correctly irrespective of 8- or 10-bit resolution. Serial data are
fed out of the serializer and into the scrambler and NRZ to NRZI circuit. The scrambler
circuit uses a linear feedback shift register, which is used to pseudo-randomize incoming
serial data. This has the effect of minimizing the DC component of the output serial data
stream, the NRZ to NRZI circuit converts long series of ones to a series of transitions.
The resulting signal contains enough information at clock rate and is suffi ciently DC free
that it may be sent down existing video cables. It may be then be reclocked, decoded,
and converted back to parallel data at the receiving equipment. Because of its very high
data rate, serial video must be carried by ECL circuits. An illustration of a typical ECL
gate is given in Figure 28.12. Note that standard video levels are commensurate with data
levels in ECL logic. Clearly the implementation of such a high-speed interface is a highly
specialized task. Fortunately, practical engineers have all the requirements for interface
encoders and decoders designed for them by third-party integrated circuit manufacturers
( Figure 28.13 ).