Audio Engineering

882 Chapter 30

from ve to –ve as the output voltage exceeds some predetermined output voltage level.
The THD given by this oscillator approaches 0.0001% at 1 kHz, worsening to about
0.0003% at the extremes of its 100-Hz to 10-kHz operating frequency range.

It is expected in modem wide-range low-distortion test bench oscillators that they will
offer a high degree of both frequency and amplitude stability. This is diffi cult to obtain
using designs based on resistor/capacitor or inductor/capacitor frequency control systems,
which has encouraged the development of designs based on digital waveform synthesis,
and other forms of digital signal processing.

30.2.2 Digital Waveform Generation

Because of the need for a precise, stable, and reproducible output signal frequency in a
test oscillator, a number of circuit arrangements have been designed in which use is made
of the frequency drift-free output obtainable from a quartz crystal oscillator. Since this
will normally provide only a single spot-frequency output, some arrangement is needed to
derive a variable frequency signal from this fi xed frequency reference source.

One common technique makes use of the “ phase locked loop ” (PLL) layout shown in
Figure 30.8. In this, the outputs from a highly stable quartz crystal “ clock ” oscillator and

Clock Divide by M

MP

PSD

Divide by N

LPF

User controls

VCO

Divider

Output

Figure 30.8 : Phase-locked loop oscillator.