Make Electronics

Experiment 19: Learning Logic

194 Chapter 4

FundAmentAls

Rules for connecting logic gates

Permitted:

• You can connect the input of a gate directly to your
  regulated power supply, either positive side or nega-
  tive side.


• You can connect the output from one gate directly to
  the input of another gate.


• The output from one gate can power the inputs of
  many other gates (this is known as “fanout”). The exact
  ratio depends on the chip, but you can always power at
  least ten inputs with one logic output. The output from
  a logic chip can drive the trigger (pin 3) of a 555 timer.

The output from the timer can then deliver 100mA,

easily enough for half-a-dozen LEDs or a small relay.

• Low input doesn’t have to be zero. A 74HCxx logic gate
  will recognize any voltage up to 1 volt as “low.”


• High input doesn’t have to be 5 volts. A 74HCxx logic
  gate will recognize any voltage above 3.5 volts as
  “high.”
  See Figures 4-75 and 4-76 for a comparison of permit-
  ted voltages on the input and output side of 74HCxx and
  74LSxx chips.

At most 0.1V

Acceptable input

signal range

Guaranteed output

signal range

Max power

consumption

at each pin:

1uA (sink)

1uA (source)

Max power

output

at each pin:

4mA (source)

4mA (sink)

5V

DC

74 HCXX

Logic Gate

Maximum 1.0V3.5VMinimum

Low High

Low High

At least 4.4V

Figure 4-75. Each family of logic chips, and each generation

in each family, has different standards for input and output

minimum and maximum voltages. This diagram shows the

standards used by the HC generation of the CMOS family,

which was chosen for most of the projects in this book. Note

that the current required for input is minimal compared with

the current available for output. The power supply to the chip

makes up the difference.

At most 0.4V

Acceptable input

signal range

Guaranteed output

signal range

Max power

consumption

at each pin:

20uA (sink)

400uA (source)

Max power

output

at each pin:

0.4mA (source)

4.0mA (sink)

5V

DC

74 LSXX

Logic Gate

2.0VMinimum

Maximum 0.8V

Low High

Low High

2.7VAt least

Figure 4-76. Because the LS generation of the TTL family has

such different tolerances for input voltages and different

standards for output voltages, the LS generation of TTL chips

should not be mixed in the same circuit as the HC generation

of CMOS chips, unless pull-up resistors are used to bring the

LS chips into conformance with standards expected by the HC

chips. See Experiment 21 for a case study in using LS chips.