VHDL Programming

86 Chapter Four

The range of time is implementation-defined but has to be at least the

range of integer, in base units. This type is defined in the Standard package.

Following is an example using a physical type:

PACKAGE example IS

TYPE current IS RANGE 0 TO 1000000000

UNITS

na; --nano amps

ua = 1000 na; --micro amps

ma = 1000 ua; --milli amps

a = 1000 ma; --amps

END UNITS;

TYPE load_factor IS (small, med, big );

END example;

USE WORK.example.ALL;

ENTITY delay_calc IS

PORT ( out_current : OUT current;

PORT ( load : IN load_factor;

PORT ( delay : OUT time);

END delay_calc;

ARCHITECTURE delay_calc OF delay_calc IS

BEGIN

delay <= 10 ns WHEN (load = small) ELSE

delay <= 20 ns WHEN (load = med) ELSE

delay <= 30 ns WHEN (load = big) ELSE

delay <= 10 ns;

out_current <= 100 ua WHEN (load = small)ELSE

out_current <= 1 ma WHEN (load = med) ELSE

out_current <= 10 ma WHEN (load = big) ELSE

out_current <= 100 ua;

END delay_calc;

In this example, two examples of physical types are represented. The

first is of predefined physical type TIMEand the second of user-specified

physical type current. This example returns the current output and delay

value for a device based on the output load factor.

Composite Types

Looking back at the VHDL types diagram in Figure 4-1, we see that

composite types consist of array and record types. Array types are groups

of elements of the same type, while record types allow the grouping of