VHDL Programming

136 Chapter Five

Declaring data inside of a package allows the data to be referenced by

other entities; thus, the data can be shared.

A package consists of two parts: a package declaration section and a

package body. The package declaration defines the interface for the package,

much the same way that the entity defines the interface for a model. The

package body specifies the actual behavior of the package in the same

method that the architecture statement does for a model.

Package Declaration

The package declaration section can contain the following declarations:

Subprogram declaration

Type, subtype declaration

Constant, deferred constant declaration

Signal declaration creates a global signal

File declaration

Alias declaration

Component declaration

Attribute declaration, a user-defined attribute (Chapter 8,

“Advanced Topics”)

Attribute specification

Disconnection specification

Use clause

All of the items declared in the package declaration section are visible

to any design unit that uses the package with a USEclause. The interface to

a package consists of any subprograms or deferred constants declared in

the package declaration. The subprogram and deferred constant declara-

tions must have a corresponding subprogram body and deferred constant

value in the package body or an error results.

Deferred Constants

Deferred constants are constants that have their name and type declared

in the package declaration section but have the actual value specified in

the package body section. Following is an example of a deferred constant

in the package declaration: