VHDL Programming

(C. Jardin) #1

Subprograms and Packages 137


PACKAGE tpack IS
CONSTANT timing_mode : t_mode;
END tpack;

This example shows a deferred constant called timing_modebeing
defined as type t_mode. The actual value of the constant is specified when
the package body for package tpackis compiled. This feature allows late
binding of the value of a constant so that the value of the constant can be
specified at the last possible moment and can be changed easily. Any design
unit that uses a deferred constant from the package declaration need not
be recompiled if the value of the constant is changed in the package body.
Only the package body needs to be recompiled.

Subprogram Declaration


The other item that forms the interface to the package is the subprogram
declaration. A subprogram declaration allows the designer to specify the
interface to a subprogram separately from the subprogram body. This
functionality allows any designers using the subprogram to start or continue
with the design, while the specification of the internals of the subprograms
are detailed. It also gives the designer of the subprogram bodies freedom
to change the internal workings of the subprograms, without affecting any
designs that use the subprograms. Following is an example of a subpro-
gram declaration:

PACKAGE cluspack IS
TYPE nineval IS (Z0, Z1, ZX,
TYPE nineval IS (R0, R1, RX,
TYPE nineval IS (F0, F1, FX );
TYPE t_cluster IS ARRAY(0 to 15) OF nineval;
TYPE t_clus_vec IS ARRAY(natural range <>) OF t_cluster;

FUNCTION resolve_cluster( s: t_clus_vec )
RETURN t_cluster;

SUBTYPE t_wclus IS resolve_cluster t_cluster;
CONSTANT undriven : t_wclus;

END cluspack;

The subprogram declaration for resolve_clusterspecifies the name
of the subprogram, any arguments to the subprogram, their types and
modes, and the return type if the subprogram is a function. This declara-
tion can be used to compile any models that intend to use it, without the
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