VHDL Programming

150 Chapter Six

LIBRARY IEEE;

USE IEEE.std_logic_1164.ALL;

ENTITY shifter IS

PORT( clk, left : IN std_logic;

right : OUT std_logic);

END shifter;

ARCHITECTURE structural OF shifter IS

COMPONENT dff

PORT( d, clk : IN std_logic;

q : OUT std_logic);

END COMPONENT;

SIGNAL i1, i2, i3: std_logic;

BEGIN

u1: dff PORT MAP(d => left, clk => clk, q => i1);

u2: dff PORT MAP(d => i1, clk => clk, q => i2);

u3: dff PORT MAP(d => i2, clk => clk, q => i3);

u4: dff PORT MAP(d => i3, clk => clk, q => right);

checktime: PROCESS(clk)

VARIABLE last_time : time := time’left;

BEGIN

ASSERT (NOW - last_time = 20 ns)

REPORT “spike on clock”

SEVERITY WARNING;

last_time := now;

END PROCESS checktime;

END structural;

The preceding example is a shift register modeled using four dffcom-

ponents connected in series. A passive process statement exists in the

architecture for entity shifter, used to detect spikes on the clkinput.

The following example shows the results of the attributes for the archi-

tecture structural:

structural’BEHAVIOR: returns false

structural’STRUCTURE: returns true

The passive process checktimehas no effect on the fact that the

architecture is structural. If the process contained signal assignment

statements, then the process would no longer be considered passive, and

attribute ’STRUCTUREwould also return false.