VHDL Programming

Predefined Attributes 165

0 102030 4050607080

A

B

Figure 6-3
Example Showing
’DELAYED (10ns).

At the first two changes in signal a(10 ns and 30 ns), signal bimme-

diately changes to false (actually at the next delta). Then when signal a

has been stable for 10 ns, signal bchanges to true. At time 55 ns, signal

achanges value again, so signal bchanges to false. Because signal a

changes 5 ns later (60 ns), signal ahas not been stable long enough to

allow output bto go to a true value. Only at 10 ns after the last change

on signal a(60 ns) is the input signal astable long enough to allow signal

bto change to true.

If the time value specified for the ’STABLEattribute is 0 ns, or not spec-

ified, then the ’STABLEattribute is false for 1 delta whenever the signal

that the attribute is attached to changes. An example of this scenario is

shown in Figure 6-4.

When used in this method, the resulting signal value has the same

timing but opposite value as function attribute ’EVENT. A statement to

detect the rising edge of a clock could be written in two ways, as shown

here:

IF (( clk’EVENT ) AND ( clk = ’ 1 ’ ) AND

( clk’LAST_VALUE = ’ 0 ’ )) THEN

.

. -- DO PROCESSING
.
END IF;

IF (( NOT( clk’STABLE) ) AND ( clk = ’ 1 ’ ) AND

(

clk’LAST_VALUE = ’ 0 ’ )) THEN

.

. --- DO PROCESSING
.
END IF;