VHDL Programming

166 Chapter Six

A

B

One Delta wide

Figure 6-4
Example Showing
’DELAYED (0 ns).

In both cases, the IFstatement detects the rising edge; but the IFstate-

ment using ’EVENTis more efficient in memory space and speed. The rea-

son for this is that attribute ’STABLEcreates an extra signal in the design

that uses more memory to store, and whenever the value for the new

signal needs to be updated, it must be scheduled. Keeping track of signal

events costs memory and time.

Attribute ’QUIET

Attribute ’QUIEThas the same functionality as ’STABLE, except that

’QUIETis triggered by transactions on the signal that it is attached to in

addition to events. Attribute ’QUIETcreates a BOOLEANsignal that is true

whenever the signal it is attached to has not had a transaction or event

for the time expression specified.

Typically, models that deal with transactions involve complex models

of devices at the switch level or the resolution of driver values. Following

is an interesting application using the attribute ’QUIET:

ARCHITECTURE test OF test IS

TYPE t_int is (int1, int2, int3, int4, int5 );

SIGNAL int, intsig1, intsig2, intsig3 : t_int;

SIGNAL lock_out : BOOLEAN;

BEGIN

int1_proc: PROCESS

BEGIN

.

.

.

WAIT ON trigger1; -- outside trigger signal

WAIT UNTIL clk = ’ 1 ’;

IF NOT(lock_out) THEN

intsig1 <= int1;

END IF;