VHDL Programming

(C. Jardin) #1

168 Chapter Six


END PROCESS;

END test;

This example shows how a priority mechanism could be modeled for an
interrupt handler. Process int1_prochas the highest priority, and process
int3_prochas the lowest. Whenever one of the processes is triggered, the
appropriate interrupt handler is placed on signal int, and the interrupt
handler for that interrupt is called.
The model consists of three processes that drive the interrupt signal
int, and another process to call the appropriate interrupt handling func-
tion.Signal intis not a resolved signal and therefore cannot have multi-
ple drivers. If a resolution function is written for signal int, the order of
the drivers cannot be used to determine priority. Therefore, the approach
shown in the preceding was taken.
In this approach, three internal signals intsig1,intsig2, and intsig3
are driven by each of the processes, respectively. These signals are then
combined, using a conditional signal assignment statement. The condi-
tional signal assignment statement makes use of the predefined attribute
’QUIETto determine when a transaction has been assigned to a driver of
a signal. It is required that transactions are detected on the internal signals,
because the process always assigns the same value so an event only occurs
on the first assignment.
The priority mechanism is controlled by the conditional signal assign-
ment statement. When a transaction occurs on intsig1,intsig2,or
intsig3, the assignment statement evaluates and assigns the appropriate
value to signal intbased on the signal(s) that had a transaction. If a
transaction occurred only on intsig2,intsig2’QUIETwould be false,
causing the conditional signal assignment statement to place the value of
intsig2on signal int. But what happens if intsig3and intsig2occur
at the same time? The conditional signal assignment statement evaluates,
and the first clause that has a WHENexpression return true does the
assignment and then exits the rest of the statement. For this example, the
value for intsig2is returned, because it is first in the conditional signal
assignment statement. The priority of the inputs is determined by the or-
der of the WHENclauses in the conditional signal assignment statement.

Attribute ’TRANSACTION


The process that implemented the interrupt handling for the previous
example uses the ’TRANSACTION attribute in a WAITstatement. This
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