VHDL Programming

(C. Jardin) #1

Chapter 7 Configurations


Configurations are a primary design unit used to bind
component instances to entities. For structural models,
configurations can be thought of as the parts list for the
model. For component instances, the configuration specifies
from many architectures for an entity which architecture
to use for a specific instance. When the configuration for
an entity-architecture combination is compiled into the
library, a simulatable object is created.
Configurations can also be used to specify generic values
for components instantiated in the architecture configured
by the configuration. This mechanism, for example, pro-
vides a late-binding capability for delay values. Delay values
calculated from a physical layout tool, such as a printed
circuit board design system or a gate array layout system,
can be inserted in a configuration to provide a simulation
model with actual delays in the design.
If the designer wants to use a component in an archi-
tecture that has different port names from the architec-
ture component declaration, the new component can have
its ports mapped to the appropriate signals. With this
functionality, libraries of components can be mixed and
matched easily.

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