VHDL Programming

(C. Jardin) #1

186 Chapter Seven


configuration sections. If no overriding values are present, the default
values are used; but if a value is mapped to the generic with a generic
map, the default value is overridden.
To see an example of this, let’s modify the decoder example, used pre-
viously in this chapter, to include two generics. The first specifies a tim-
ing mode to run the simulation, and the second is a composite type
containing the delay values for the device. These two types are declared
in the package p_time_pack, as shown in the following:

LIBRARY IEEE;

USE IEEE.std_logic_1164.ALL;
PACKAGE p_time_pack IS
TYPE t_time_mode IS (minimum, typical, maximum);
TYPE t_rise_fall IS
RECORD
rise : TIME;
fall : TIME;
END RECORD;

TYPE t_time_rec IS ARRAY(t_time_mode’LOW TO
t_time_mode’HIGH) OF t_rise_fall;

FUNCTION calc_delay(newstate : IN std_logic; mode : IN
t_time_mode;
delay_tab : IN t_time_rec ) return time;

END p_time_pack;

PACKAGE BODY p_time_pack IS
FUNCTION calc_delay(newstate : IN std_logic; mode : IN
t_time_mode;
delay_tab : IN t_time_rec ) return time IS
BEGIN
CASE f_state(newstate) IS
WHEN ‘ 0 ’ =>
RETURN delay_tab(mode).fall;
WHEN ‘ 1 ’ =>
RETURN delay_tab(mode).rise;
WHEN ‘X’ =>
IF (delay_tab(mode).rise <= delay_tab(mode).fall) THEN
RETURN delay_tab(mode).rise;
ELSE
RETURN delay_tab(mode).fall;
END IF;
END CASE;
END calc_delay;
END p_time_pack;

This package declares types t_time_modeand t_time_rec, which are
used for the generics of the inverter and 3-input AND gates. It also includes
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