VHDL Programming

(C. Jardin) #1

188 Chapter Seven


After the entities and architectures for the gates have been defined,
configurations that provide specific values for the generics are defined.
These models can have their generic values specified by two methods.
The first method is to specify the generic values in the architecture where
the components are being instantiated. The second method is to specify
the generic values in the configuration for the model, where the compo-
nents are instantiated.

Generic Value Specification in Architecture


Specifying the generic values in the architecture of an entity allows the
designer to delay the specification of the generic values until the archi-
tecture of the entity is created. Different generic values can be specified
for each instance of an entity allowing one entity to represent many dif-
ferent physical devices. Following is an example of an architecture with
the generic values specified in it:

ARCHITECTURE structural OF decode IS
COMPONENT inv
GENERIC( mode : t_time_mode;
GENERIC( delay_tab : t_time_rec);
PORT( a : IN std_logic;
PORT( b : OUT std_logic);
END COMPONENT;

COMPONENT and3
GENERIC( mode : t_time_mode;
GENERIC( delay_tab : t_time_rec);
PORT( a1, a2, a3 : IN std_logic;
PORT( o1 : OUT std_logic);
END COMPONENT;

SIGNAL nota, notb : std_logic;
BEGIN
I1 : inv
GENERIC MAP( mode => maximum,
delay_tab => ((1.3 ns, 1.9 ns),
delay_tab => ((2.1 ns, 2.9 ns),
delay_tab => ((3.2 ns, 4.1 ns)))
PORT MAP( a, nota );

I2 : inv
Free download pdf