4 Chapter One
The keyword ENTITYsignifies that this is the start of an entity state-
ment. In the descriptions shown throughout the book, keywords of the
language and types provided with the STANDARD package are shown in
ALL CAPITAL letters. For instance, in the preceding example, the key-
words are ENTITY, IS, PORT, IN, INOUT, and so on. The standard type pro-
vided is BIT. Names of user-created objects such as mux, in the example
above, will be shown in lower case.
The name of the entity is mux. The entity has seven ports in the PORT
clause. Six ports are of mode INand one port is of mode OUT. The four data
input ports (a, b, c, d) are of type BIT. The two multiplexer select inputs,
s0and s1, are also of type BIT. The output port is of type BIT.
The entity describes the interface to the outside world. It specifies
the number of ports, the direction of the ports, and the type of the ports.
A lot more information can be put into the entity than is shown here,
but this gives us a foundation upon which we can build more complex
examples.Architectures
The entity describes the interface to the VHDL model. The architec-
ture describes the underlying functionality of the entity and contains
the statements that model the behavior of the entity. An architecture is
always related to an entity and describes the behavior of that entity. An
architecture for the counter device described earlier would look like this:ARCHITECTURE dataflow OF mux IS
SIGNAL select : INTEGER;
BEGIN
select <= 0 WHEN s0 = ‘0’ AND s1 = ‘0’ ELSE
1 WHEN s0 = ‘1’ AND s1 = ‘0’ ELSE
2 WHEN s0 = ‘0’ AND s1 = ‘1’ ELSE
3;x <= a AFTER 0.5 NS WHEN select = 0 ELSE
b AFTER 0.5 NS WHEN select = 1 ELSE
c AFTER 0.5 NS WHEN select = 2 ELSE
d AFTER 0.5 NS;END dataflow;The keyword ARCHITECTUREsignifies that this statement describes an
architecture for an entity. The architecture name is dataflow. The entity
the architecture is describing is called mux.