212 Chapter Eight
PORT( c : IN INTEGER;
PORT( dout : OUT INTEGER);
END adder;ARCHITECTURE test OF adder IS
SIGNAL internal : INTEGER;
BEGIN
internal <= a + b;
dout <= c + internal;
END test;This example illustrates how overloading can be used to make very
readable models. The value assigned to signal internalis the sum of
inputs aand b. Since aand bare of type BIT_VECTOR, the overloaded
operator function that has two BIT_VECTORarguments is called. This func-
tion adds the values of aand btogether and returns an integer value to
be assigned to signal internal.
The second addition uses the standard built-in addition function that
is standard in VHDL because both operands are of type INTEGER. This
model could have been written as shown in the following, but would still
function in the same manner:PACKAGE math IS
FUNCTION addvec( l,r : bit_vector) RETURN INTEGER;
END math;PACKAGE BODY math IS
FUNCTION vector_to_int( S : bit_vector) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE prod : INTEGER := 1;
BEGIN
FOR i IN s’RANGE LOOP
IF s(i) = ‘ 1 ’ THEN
result := result + prod;
END IF;
prod := prod * 2;
END LOOP;
RETURN result;
END vector_to_int;FUNCTION addvec(l,r : bit_vector) RETURN INTEGER IS
BEGIN
RETURN ( vector_to_int(l) + vector_to_int(r));
END addvec;
END math;USE WORK.math.ALL;
ENTITY adder IS
PORT( a, b : IN BIT_VECTOR(0 TO 7);
PORT( c : IN INTEGER;