VHDL Programming

(C. Jardin) #1

Advanced Topics 213


PORT( dout : OUT INTEGER);
END adder;

ARCHITECTURE test2 OF adder IS
SIGNAL internal : INTEGER;
BEGIN
internal <= addvec(a,b);
dout <= c + internal;
END test2;

In this example, a function called advecis used to add aand b. Both
coding styles give exactly the same results, but the first example using
the overloaded +operator is much more readable and easier to maintain.
If another person besides the designer of a model takes over the mainte-
nance of the model, it is much easier for the new person to understand
the model if overloading was used.

OPERATOR ARGUMENT TYPE OVERLOADING Arguments to
overloaded operator functions do not have to be of the same type, as the
previous two examples have shown. The parameters to an overloaded
operator function can be of any type. In some cases, it is preferable to
write two functions so that the order of the arguments is not important.

Let’s examine the functions for an overloaded logical operator that mixes
signals of type BITand signals of a nine-state value system:

PACKAGE p_logic_pack IS
TYPE t_nine_val IS (Z0, Z1, ZX,
TYPE t_nine_val IS (R0, R1, RX,
TYPE t_nine_val IS (F0, F1, FX);

FUNCTION “AND”( l, r : t_nine_val) RETURN BIT;

FUNCTION “AND”( l : BIT; r : t_nine_val) RETURN BIT;

FUNCTION “AND”( l : t_nine_val; r : BIT) RETURN BIT;

END p_logic_pack;

PACKAGE BODY p_logic_pack IS
FUNCTION nine_val_2_bit( t : IN t_nine_val) RETURN BIT IS
TYPE t_nine_val_conv IS ARRAY(t_nine_val) OF BIT;
CONSTANT nine_2_bit : t_nine_val_conv :=
(‘ 0 ’, — Z0
‘ 1 ’, — Z1
‘ 1 ’, — ZX
‘ 0 ’, — R0
‘ 1 ’, — R1
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