220 Chapter Eight
The package p_attrdefines the type used for one of the attributes and
contains the attribute declarations for two attributes. The attribute
declarations make the name and type of the attribute visible to any
object for use if needed.
In the architecture cpu_boardof entity boardare the attribute speci-
fications. The attribute specification describes the attribute name to be
used, the name of the object to which the attribute is attached, the object
kind, and finally the value of the attribute.
To access the value of a user-defined attribute, use the same syntax for
a predefined attribute. In the signal assignment statements of architec-
ture cpu_board, the attribute value is retrieved by specifying the name of
the object, followed by a ’and the attribute name.Generate Statements
Generate statements give the designer the ability to create replicated
structures, or select between multiple representations of a model. Generate
statements can contain IF-THENand looping constructs, nested to any
level, that create concurrent statements.
Typical applications include memory arrays, registers, and so on.
Another application is to emulate a conditional compilation mechanism
found in other languages such as C.
Following is a simple example showing the basics of generate statements:LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY shift IS
PORT( a, clk : IN std_logic;
PORT( b : OUT std_logic);
END shift;ARCHITECTURE gen_shift OF shift IS
COMPONENT dff
PORT( d, clk : IN std_logic;
PORT( q : OUT std_logic);
END COMPONENT;SIGNAL z : std_logic_vector( 0 TO 4 );
BEGIN
z(0) <= a;g1 : FOR i IN 0 TO 3 GENERATE
dffx : dff PORT MAP( z(i), clk, z(i + 1));