224 Chapter Eight
GENERIC( setup, qrise, qfall, qbrise, qbfall : time);
PORT( din, clk : IN std_logic;
PORT( q, qb : OUT std_logic);
END dff;ARCHITECTURE condition OF dff IS
BEGIN
G1 : IF (timing_checks = onn) GENERATE
ASSERT ( din’LAST_EVENT >>setup)
REPORT “setup violation”
SEVERITY ERROR;
END GENERATE;PROCESS(clk)
VARIABLE int_qb : std_logic;
BEGIN
IF (clk = ‘ 1 ’) AND (clk’EVENT) AND (clk’LAST_VALUE =
‘ 0 ’) THEN
int_qb := not din;q <= din AFTER f_delay( din, qrise, qfall);qb <= int_qb AFTER f_delay( int_qb, qbrise, qbfall);
END IF;
END PROCESS;
END condition;In this example, a DFFcomponent is modeled using a generate state-
ment to control whether or not a timing check statement is generated for
the architecture. The generic,timing_checks, can be passed a value of onn
or off. (Note the spelling of onn. We cannot use a value of on because it
is a reserved word.) If the value is onn, then the generate statement
generates a concurrent assertion statement. If the value of generic
timing_checksis off, then no assertion statement is generated. This
functionality emulates the conditional compilation capability of some
programming languages, such as C and Pascal.TextIO
One of the predefined packages that is supplied with VHDL is the
Textual Input and Output (TextIO) package. The TextIO package contains
procedures and functions that give the designer the ability to read from
and write to formatted text files. These text files are ASCII files of any
format that the designer desires. (VHDL does not impose any limits of
format, but the host machine might impose limits.) TextIO treats these