VHDL Programming

232 Chapter Nine

RTL

Description

Constraints

Synthesis

Technology

Library

Gate Level

Netlists

Figure 9-1
Gate Level Netlist
Synthesis.

These gate level netlists currently can be optimized for area, speed,

testability, and so on. The synthesis process is shown in Figure 9-1.

The inputs to the synthesis process are an RTL (Register Transfer

Level) VHDL description, circuit constraints and attributes for the design,

and a technology library. The synthesis process produces an optimized gate

level netlist from all of these inputs. In the next few sections, each of these

inputs is described, and we discuss the synthesis process in more detail.

Register Transfer Level Description

A register transfer level description is characterized by a style that spec-

ifies all of the registers in a design, and the combinational logic between.

This is shown by the register and cloud diagram in Figure 9-2. The reg-

isters are described either explicitly through component instantiation or

implicitly through inference. The registers are shown as the rectangular

objects connected to the clock signal. The combinational logic is described

by logical equations, sequential control statements (CASE,IF then ELSE,

and so on), subprograms, or through concurrent statements, which are

represented by the cloud objects between registers.