VHDL Programming

238 Chapter Nine

There are a number of constraints shown on the diagram including

required time constraints, late arrival constraints, and clock cycle con-

straints.

Required time constraints specify the latest time that a signal can occur.

Clock constraints are used to specify the operating frequency of the clock.

From the clock constraint, required time constraints of each signal feeding

a clocked register can be calculated. Each of these constraints is further

described in the next sections.

Timing Constraints

Typical uses for timing constraints are to specify maximum delays for

particular paths in a design. For instance, a typical timing constraint is

the required time for an output port. The timing constraint guides the

optimization and mapping to produce a netlist that meets the timing

constraint. Meeting timing is usually one of the most difficult tasks when

designing an ASIC or FPGA using synthesis tools. There may be no design

that meets the timing constraints specified. A typical delay constraint in

Leonardo synthesis format is shown here:

set_attribute -port data_out -name required_time -value 25

This constraint specifies that the maximum delay for signal data_out

should be less than or equal to 25 library units. A library unit can be

whatever the library designer used when describing the technology from

a synthesis point of view. Typically, it is nanoseconds, but can be picoseconds

or some other time measurement depending on the technology.

Clock Constraints

One method to constrain a design is to add a required_timeconstraint

to every flip-flop input with the value of a clock cycle. The resulting

design would be optimized to meet the one clock cycle timing constraint.

An easier method, however, is to add a clock constraint to the design. A

clock constraint effectively adds an input required_timeconstraint to

every flip-flop data input. An example clock constraint is shown here:

set_attribute -port clk -name clock_cycle -value 25