VHDL Synthesis 261
Asynchronous Preset and Clear
Is it possible to describe a flip-flop with an asynchronous presetand
clear? As an attempt, we can use the same technique as in the asyn-
chronous resetexample. The following example illustrates an attempt to
describe a flip-flop with an asynchronous presetand clearinputs:LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY dff_pc IS
PORT( preset, clear, clock, din : IN std_logic;
PORT( dout : OUT std_logic);
END dff_pc;ARCHITECTURE synth OF dff_pc IS
BEGIN
PROCESS(preset, clear, clock)
BEGIN
IF (preset = ‘ 1 ’) THEN
dout <= ‘ 1 ’;ELSEIF (clear = ‘ 1 ’) THEN
dout <= ‘ 0 ’;ELSEIF (clock’EVENT) AND (clock = ‘ 1 ’) THEN
dout <= din;END IF;
END PROCESS;
END synth;The entity contains a presetsignal that sets the value of the flip-flop
to a ‘ 1 ’, a clear signal that sets the value of the flip-flop to a ‘ 0 ’, and the
normal clockand dinports used for the clocked D flip-flop operation. The
architecture contains a single process statement with a single IFstate-
ment to describe the flip-flop behavior. The IFstatement assigns a ‘ 1 ’to
the output for a ‘ 1 ’value on the presetinput and a ‘ 0 ’to the output
for a ‘ 1 ’on the clearinput. Otherwise, the clockinput is checked for a
rising edge, and the dinvalue is clocked to the output dout.
What does the output of the synthesis process produce for this VHDL
input? The output is shown in Figure 10-8. We were expecting the output
of the synthesis tool in which the design presetinput was connected to
the presetinput of the flip-flop, and the design clearinput was con-
nected to the clearinput of the flip-flop. The output from the synthesis
tool is a design in which the design presetand clearinputs are sepa-
rated from the flip-flop presetand clearinputs by some logic.