High-Level Design Flow 281
NAME GATE ARRIVAL LOAD
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modgen_0_l1_l0_l0_5_l0_c5/Y CARRY 5.40 up 0.00
modgen_0_l1_l0_l0_6_l0_c1/Y AND2 5.40 up 0.00
modgen_0_l1_l0_l0_6_l0_c3/Y OR2 5.40 up 0.00
modgen_0_l1_l0_l0_6_l0_c4/Y OR2 5.40 up 0.00
modgen_0_l1_l0_l0_6_l0_c5/Y CARRY 5.90 up 0.00
modgen_0_l1_l0_l0_7_l0_sum0/Y XOR2 5.90 up 0.00
modgen_0_l1_l0_l0_7_l0_sum1/Y XOR2 5.90 up 0.00
modgen_0_l1_l0_l0_7_l0_sum2/Y LCELL 10.00 up 0.00
ix39/OUT OUTBUF 13.80 up 0.00
c(7)/ 13.80 up 0.00
data arrival time 13.80In this report, the worst-case path is listed shown with estimated time
values for each node traversed in the design. The timing analyzer calcu-
lates the time for a path from an input pin to a flip-flop or output, or from
a flip-flop output to a flip-flop input, or output pin.
The designer has the ability to ask for the timing for particular paths
of interest, or of the paths that have the longest timing value, and how
many to display. As mentioned previously, the worst-case paths ultimately
determine the speed of the design. For instance, in this case, the worst-
case path is 13.8 nanoseconds; therefore, the fastest this design would be
able to run is about 72 MHz.
The last type of output data that the designer can examine is the
netlist for the design in the target technology. This output is a gate or
macro-level output in a format compatible with the place and route
tools that are used to implement the design in the target chip. For in-
stance, most place and route tools for FPGA technologies take in an
EDIF netlist as an input format. The primitives used in the netlist are
those used in the synthesis library to describe the technology. The place
and route tools understand what to do with these primitives in terms
of how to place a primitive and how to route wires to them. The
following example uses a VHDL netlist for ease of understanding. To
save space (and boredom), this is not a complete netlist, but gives the
reader an idea of how a netlist is structured. The complete netlist can
be found on the included CD:--
-- Definition of adder
--
--library IEEE, EXEMPLAR; use IEEE.STD_LOGIC_1164.all; use